1. Field of the Invention
The present invention relates to a MIS (Metal Insulator Semiconductor) transistor type semiconductor memory device having a two-layer gate electrode made up of a floating gate and a control gate. In particular, the invention can be preferably applied to EPROMs, EEPROMs, flash EEPROMS, and the like.
2. Related Arts
A flash memory is widely known as a nonvolatile semiconductor memory capable of electrically writing and erasing information therein. Such a flash memory generally includes a floating gate provided on a substrate through a first gate insulating layer (a tunnel layer) and a control gate provided on the floating gate through a second gate insulating layer. Further, source and drain are provided in a surface region of the substrate to face both ends of the control gate.
Next, typical operations, i.e., (a) a reading operation, (b) a writing operation, and (c) an erasing operation, of the cell of the flash memory will be explained with reference to FIGS. 1A, 1B, and 1C. When the reading operation is carried out, a positive voltage in a range of 1 to 2 V is applied to the drain, the source is grounded, and a voltage Vcc is applied to the control gate as shown in FIG. 1A. In this state, readout of the information is performed by detecting if a channel current flows. When the writing operation is carried out, the voltage Vcc is applied to the drain, the source is grounded, and a positive high voltage Vpp of, for example, +12 V is applied to the control gate as shown in FIG. 1B. Accordingly, hot electrons are injected into the floating gate from between a channel and the drain through the tunnel layer by a tunnel effect. Further, when erasing operation is carried out, the voltage vcc is applied to the source, the drain is opened, and a negative high voltage Vpp is applied to the control gate as shown in FIG. 1C. Accordingly, the electrons stored in the floating gate are extracted and injected into the source by the tunnel effect.
In general, as shown in FIG. 2, a flash memory 100 includes a large number of bits arrayed in a matrix. When the above-mentioned writing and erasing operations are performed on the flash memory 100, a voltage is applied not only to terminals of bits that are selected (herebelow referred to as selected bits) but to terminals of the other bits (herebelow referred to as non-selected bits). As a result, the non-selected bits charges sometimes move between charge holding parts of the bits and the terminals to which the voltage is applied so that memories stored in the non-selected bits are erased.
This phenomenon is called disturbance in a nonvolatile memory. A particular type of this disturbance is drain disturbance, which arises when a voltage is applied to a drain of a non-selected bit under the writing operation. This drain disturbance phenomenon is further explained with reference to FIG. 3 showing the non-selected bit under the writing operation. Specifically, the source is grounded and the voltage V.sub.cc acts on the drain. Further, the control gate is on a ground level because it is not selected. In this state, by unintentionally applying an extra voltage to the terminal of the drain, a drain side end portion of the gate oxide layer underlying the floating gate is subject to an electrical field having a high field intensity. Consequently, there arises a possibility that the electrons are extracted from the floating gate through the gate oxide layer. This is the drain disturbance phenomenon. It is considered that because a drain side edge of the floating gate is angular, an electric field is likely to be concentrated on the angular edge of the floating gate and the drain disturbance sometimes results.
To avoid this, JP-A-5-29962, JP-A-6-237004, and the like disclose a method for preventing the drain disturbance by chamfering the drain side edge of the floating gate to mitigate the concentration of the electric field on the edge. However, as a result of experiments performed by the inventors, it was found that the drain disturbance could not be sufficiently prevented only by chamfering the drain side edge of the floating gate.